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Author Enomoto, Tadayoshi ♦ Kobayashi, Nobuaki
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Cmos Square-root Circuit ♦ Low Dynamic Power ♦ Low Leakage Power ♦ New Architecture ♦ New Algorithm ♦ Dynamic Power ♦ Conventional Sr Circuit ♦ Cmos Square-root ♦ 90-nm Cmos Lsi ♦ New Sr Circuit ♦ Leakage Power ♦ Simulated Result ♦ New Leakage Reduction Circuit
Abstract Abstract- To drastically reduce the dynamic power (PAT) and the leakage power (PST), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT and PST of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results. 1.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article