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Author Gordon-Ross, Ann ♦ Zhang, Chuanjun ♦ Vahid, Frank ♦ Dutt, Nikil
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Memory Hierarchy ♦ Configurable Parameter ♦ Static Energy Dissipation ♦ Simulation-based Exploration Environment ♦ Onchip Hardware ♦ Low-energy Embedded System ♦ Configurable Level-one Cache ♦ Data Cache Memory ♦ Line Size ♦ Frequent Value ♦ Good Candidate ♦ Total Size ♦ Energy Optimization ♦ Single-level Cache ♦ Victim Buffer ♦ On-chip Data Cache ♦ Two-level Cache ♦ Hardware-based System ♦ Efficient Cache ♦ Cache Subsystem ♦ Total Microprocessor System Power
Abstract The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for power and energy optimizations. We discuss four methods for tuning a microprocessors' cache subsystem to the needs of any executing application for low-energy embedded systems. We introduce onchip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune a configurable level-one cache's total size, associativity and line size to an executing application. We extend the single-level cache tuning heuristic for a two-level cache using a methodology applicable to both a simulation-based exploration environment and a hardware-based system prototyping environment. We show that a victim buffer can be very effective as a configurable parameter in a memory hierarchy. We reduce static energy dissipation of on-chip data cache by compressing the frequent values that widely exist in a data cache memory.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study