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Author Zhu, Huibiao ♦ Bowen, Jonathan P. ♦ Jifeng, He
Source CiteSeerX
Content type Text
Publisher Springer-Verlag
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Semantic View ♦ Operational Semantics ♦ Unified Set ♦ Hardware Description Language Verilog ♦ Denotational Semantics ♦ Ultimate Aim ♦ Algebraic Law ♦ Discrete Time Semantic Model
Description Proc. CHARME 2001: 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods
This paper presents the derivation of a denotational semantics from an operational semantics for a subset of the widely used hardware description language Verilog. Our aim is to build an equivalence between the operational and denotational semantics. We propose a discrete time semantic model for Verilog. Algebraic laws are also investigated in this paper, with the ultimate aim of providing a unified set of semantic views for Verilog. 1
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2001-01-01