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Author Goglin, Brice ♦ Bordeaux, Inria ♦ France, Sud-Ouest
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Traditional Ethernet Hardware ♦ Mmu Notifiers ♦ Myrinet Express ♦ Many Installation ♦ Corresponding Software Feature ♦ Open-mx Stack ♦ High-performance Cluster ♦ Generic Ethernet Hardware ♦ Pm Ethernet-hxb ♦ New Innovative Optimization ♦ Generic Ethernet Layer ♦ Pinning Requirement ♦ High-performance Mpi ♦ Zero-copy Model ♦ Standard Hardware ♦ High-speed Network ♦ Memory Pinning ♦ High-speed Networking ♦ Tcp Ip Stack ♦ Decoupled On-demand ♦ Overlapped On-demand Pinning ♦ Many Project ♦ Mpi Standard ♦ Application Interface ♦ Wire Protocol ♦ Open-mx Driver
Description While high-speed networks have been dominating in high-performance clusters, there are still many installations that rely on traditional ETHERNET hardware. The MPI standard has been successfully implemented on top of these technologies but its performance is limited by the TCP/IP stack which was not designed for this context. Moreover, a convergence between high-speed networks and ETHERNET is expected in the coming years. It raises the question of which features will become legacy. Therefore, many projects targeted the design of a high-performance MPI on top of generic ETHERNET hardware, such as GAMMA [2], EMP [13], or PM/ETHERNET-HXB [14]. OPEN-MX [4] offers such an implementation. It exposes the Myrinet Express [10] wire protocol and application interface by implementing the corresponding software features on top of the generic ETHERNET layer. While using standard hardware, OPEN-MX has to rely on memory pinning since it tries to mimic the zero-copy model of high-speed networks. However, its pinning requirements are simpler due to less hardware being involved. We thus envision new innovative optimizations based on the idea that pinning has to be managed by the OPEN-MX driver and does not need to be exhibited to user-space or to the hardware. The paper is organized as follows. We first describe in Section 2 how memory pinning is involved in I/O, and high-speed networking in particular. We then detail the OPEN-MX stack and why we chose to optimize its pinning. The design of our decoupled on-demand and overlapped memory pinning is then presented in Section 3. Performance is then detailed in Secinria-00356236,
In 9th Workshop on Communication Architecture for Clusters (CAC'09), Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium (IPDPS'09
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Date 2009-01-01