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Author Zhang, Wangyuan ♦ Li, Tao
Source CiteSeerX
Content type Text
File Format PDF
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Additional Power Overhead ♦ Integration Technology ♦ Phase Change Memory ♦ Memory Latency ♦ Power Density ♦ Charge Leakage ♦ Direct Placement ♦ On-chip Temperature ♦ Analytical Model ♦ Exponential Rise ♦ Low Power ♦ Refresh Frequency ♦ Power Thermal Friendly ♦ Phase-change Random Access Memory ♦ Bandwidth Constraint ♦ Die-stacked Dram ♦ Promising Candidate ♦ Upcoming 3d-stacking Technology Era ♦ Durable Memory Architecture ♦ Thermal Friendly Memory System Architecture
Description Emerging three-dimensional (3D) integration technology allows for the direct placement of DRAM on top of a microprocessor, significantly reducing the wire-delay between the two and thereby alleviating memory latency and bandwidth constraints. However, the increase in power density of 3D technology leads to elevated on-chip temperature, which results in an exponential rise in charge leakage of DRAM. Consequently, the refresh frequency of 3D die-stacked DRAM needs to be doubled (or more) to retain data at the expense of additional power overhead. In this work, we investigate using Phase-change Random Access Memory (PRAM) as a promising candidate to achieve scalable, low power and thermal friendly memory system architecture in the upcoming 3D-stacking technology era. Using analytical model, circuit- and
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study
Learning Resource Type Article
Publisher Institution In International Conference on Parallel Architectures and Compilation Techniques (PACT), 2009