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Author Vittal, K. Satyanarayana ♦ Raj, P. Cyril Prasanna ♦ Ramesh, Pillem ♦ Aravind, B. V. ♦ Fazal ♦ Noorbasha, Fazal
Source CiteSeerX
Content type Text
File Format PDF
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Image Compression ♦ Sub Circuit ♦ Performance Analysis ♦ Analog Sub Circuit ♦ Dac Implementation ♦ Current Reference ♦ Optimum Geometry ♦ Cmos Technology ♦ Multimedia Application ♦ Schematic Captured ♦ Cadence Virtuoso ♦ Prominent Signal Processing Area ♦ Building Block ♦ Artificial Neural Network
Abstract Image compression is one of the prominent signal processing areas for multimedia applications. Compressed images when transmitted are affected by noise and thus reconstruction of images at the receiver becomes complex. Very recently Artificial Neural Networks are being used for image compression and decompression. One of the building blocks in ANN is the multiplying DAC. In this paper, we present the design and analysis of sub circuits for multiplying DAC using 180nm CMOS technology. The DA, current reference and opamp are design, modelled and analysed for its performances using Cadence Virtuoso and HSPICE. The optimum geometries for sub circuits are computed and schematic captured is carried out. The results obtained show that the designed sub circuits are suitable for multiplying DAC implementation.
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research
Education Level UG and PG ♦ Career/Technical Study