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Author Datta, Kushal ♦ Mukherjee, Arindam ♦ Ravindran, Arun
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Automatic synmthesis ♦ Optimization
Abstract We present an automated design flow for minimizing the use of diodes and switches (active devices) in design implementations on a nanofabric based on chemically self-assembled electronic nanotechnology as proposed in Goldstein and Budiu [2001]. Connectivity and logic in the nanofabric are realized using the switch and diode behaviors of molecular devices, unlike very large scale integrated (VLSI) circuits where complementary metal-oxide semiconductor (CMOS) gates are used. Similar to the optimization goal of reducing the number of gates in VLSI designs to minimize area, power dissipation, and delay, decreasing the number of switches and diodes used in the nanofabric can potentially minimize design implementation area and power dissipation, besides reducing the delay and signal drop between latched stages in order to improve performance. An integrated placement, topology selection, and routing approach for design implementation on the nanofabric is proposed. Note that this problem is fundamentally different from CMOS VLSI placement and routing because of the inherent routing-dependent logic realization in our target nanofabric. To the best of our knowledge this is the first reported work on automated integrated placement, topology selection, and routing for diode-based nanofabrics. A practical and scalable simulated annealing-based placement and routing algorithm has been implemented. On average, the integrated placement and routing approach achieves a reduction of 12% in the number of switches and diodes used for MCNC benchmarks, compared to separate placement and routing optimization results. The maximum reduction achieved in the number of active devices using our approach is 24%, and in general, we observed that the bigger the benchmark, the larger the improvement achieved.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-07-01
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 2
Issue Number 3
Page Count 23
Starting Page 219
Ending Page 241


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Source: ACM Digital Library