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Author Dosho, S. ♦ Yanagisawa, N. ♦ Matsuzawa, A.
Sponsorship IEEE Solid-State Circuits Society ♦ IEEE Electron Devices Society ♦ IEEE Circuits and Systems Society ♦ IEEE Electron Devices Society ♦ IEEE Solid-State Circuits Society ♦ IEEE Solid-State Circuits Society ♦ Japan Society of Applied Physics (JSAP) ♦ IEEE Solid-State Circuits Society ♦ IEEE Solid-State Circuits Society ♦ IEEE Microwave Theory and Techniques Society ♦ IEEE Solid-State Circuits Society ♦ IEEE San Francisco Section ♦ Bay Area Council ♦ Univ. PA ♦ IEEE
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1966
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Optimization methods ♦ Phase locked loops ♦ Phase measurement ♦ Jitter ♦ Circuits ♦ Voltage-controlled oscillators ♦ Time measurement ♦ Clocks ♦ Performance analysis ♦ Calibration ♦ phase-locked loop (PLL) ♦ Background ♦ CMOS ♦ noise suppression ♦ optimization ♦ phase jitter
Abstract This paper describes a background (BG) optimization method for a phase-locked loop (PLL) by changing the circuit parameters of the PLL circuits. Measuring the phase shift of the voltage-controlled oscillator (VCO) at each input reference clock, we can determine the phase jitter performance with accuracy equal to a time interval analyzer (TIA). Using the combination of the global optimization method at initial stage and the local optimization method for the background calibration always gives the PLL the smallest jitter performance under process variation, supply voltage modulation, and temperature variation. The test environment fabricated by the 0.15-/spl mu/m CMOS controlled by an external FPGA demonstrates enough ability to suppress the impacts of the environmental variations.
Description Author affiliation :: Semicond. Co., Matsushita Electr. Ind. Co., Ltd., Osaka, Japan
ISSN 00189200
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-04-01
Publisher Place U.S.A.
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Volume Number 40
Issue Number 4
Size (in Bytes) 1.29 MB
Page Count 10
Starting Page 941
Ending Page 950


Source: IEEE Xplore Digital Library