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Author Kim, Moon Seok ♦ Cane-Wissing, William ♦ Li, Xueqing ♦ Sampson, Jack ♦ Datta, Suman ♦ Gupta, Sumeet Kumar ♦ Narayanan, Vijaykrishnan
Source ACM Digital Library
Content type Text
Publisher Association for Computing Machinery (ACM)
File Format PDF
Copyright Year ©2016
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword FinFET ♦ Standard cell ♦ And parasitic resistance ♦ Area ♦ Asymmetric vertical TFET ♦ Layout ♦ Parasitic capacitance ♦ Tunnel FET
Abstract Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome the scaling limits and to improve on-current $(I_{ON})$ compared to standard lateral device structures for the future technologies. The benefits in terms of reduced footprint, high $I_{ON}$ and feasibility of fabrication have been demonstrated in several works. Among various VTFETs, the asymmetric heterojunction vertical tunnel FETs (HVTFETs) have emerged as one of the promising alternatives to standard transistors for low-voltage applications. However, while such device-level benefits without parasitics have been widely investigated, logic-gate design with parasitics and layout implications are not clear. In this article, we investigate and compare the layouts and parasitic capacitances and resistances of HVTFETs with FinFETs. Due to the vertical device structure of HVTFETs, a smaller footprint is observed compared to FinFETs in cells with small fan-in. However, for high fan-in cells, HVTFETs exhibit area overheads due to infeasibility of contact sharing in parallel and series transistors. These area overheads also lead to approximately 48% higher parasitic capacitance and resistance compared to FinFETs when the number of parallel and series connections increases. Further, in order to analyze the impact of parasitics, we modeled the analytical parasitics in SPICE. The models for both HVTFETs and FinFETs with parasitics were used to simulate a 15-stage inverter-based ring oscillator (RO) in order to compare the delay and energy. Our simulation results clearly show that HVTFETs exhibit less delay at a $V_{DD}$ < 0.45 V and higher energy efficiency for $V_{DDs}$ in the range of 0.3V--0.7V, albeit at the cost of 8% performance degradation.
ISSN 15504832
Age Range 18 to 22 years ♦ above 22 year
Educational Use Research
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2016-05-01
Publisher Place New York
e-ISSN 15504840
Journal ACM Journal on Emerging Technologies in Computing Systems (JETC)
Volume Number 12
Issue Number 4
Page Count 23
Starting Page 1
Ending Page 23

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Source: ACM Digital Library