|Author||Ojha, Apoorva ♦ Chauhan, Yogesh Singh ♦ Mohapatra, Nihar Ranjan|
|Publisher||IEEE Xplore Digital Library|
|Subject Keyword||Stress Profile ♦ Semiconductor Device Modeling ♦ Process-induced Strain ♦ High-k Gate Dielectrics ♦ Threshold Voltage ♦ Stress Liner|
|Abstract||In this paper, a physics based compact model for the longitudinal and transverse stress profile in the channel of an uniaxially strained bulk MOS transistor is presented. The stress in the channel of a MOS transistor is not uniform and this non-uniform stress distribution results in higher average channel stress with reduction in the gate length. The developed model accurately predicts the average channel stress for different stress liners and transistor dimensions like gate length, gate height and spacer width. The modeled average stress is then used to calculate the strain induced threshold voltage shift in HKMG nMOS transistors for different stress liners (fixed transistor dimensions) and for different transistor dimensions (fixed stress liner). The accuracy of the model is verified by comparing the threshold voltage shift with the experimental data obtained from the transistors fabricated in the 28nm HKMG CMOS technology.|
|Learning Resource Type||Article|
|Journal||IEEE Journal of the Electron Devices Society|
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